Integrated semiconductor circuits, particularly transistor arrays and memories having single transistor cells each of which represents a binary bit of information, as in read only memories (ROM), have achieved high device-per-cell densities. U.S. Pat. No. 4,193,125 describes a read only memory having a P-type substrate and a plurality of N+ type diffusion layers arranged checker-wise on one major surface of the substrate in which four N+-type diffusion layers having contacts are located at the corners of an imaginary rectangle and a fifth N+-type region having a contact formed substantially at the center of the imaginary rectangle. Between the fifth N+-type diffusion layer and the first to fourth N+-type diffusion layers, four MOS transistors are formed for the single contact. Gate lines are provided, each extending between adjacent two N+-type diffusion layers without overlapping them. Each of the four N+-type diffusion layers also acts as a central N+-type region of another imaginary rectangle adjacent to the first-mentioned imaginary rectangle. This patent teaches high-density, single polysilicon layout technique.
U.S. Pat. No. 4,287,571, assigned to the assignee of the present application, describes an array of transistors suitable for use in a read only memory including a plurality of spaced-apart first conductive lines insulated from a semiconductor substrate and a plurality of spaced-apart second conductive lines insulated from the substrate and from the first lines and disposed to intersect the first lines. Diffusion regions formed in the substrate as current carrying electrodes are defined by the first and second lines. A plurality of spaced-apart third conductive lines are arranged to intersect the first and second lines and to connect to the diffusion regions. When the array is used in a read only memory, selected transistors of the array are made to have a different threshold voltage from that of the remaining transistors and the first and second lines form word lines, the third lines form bit or sense and ground lines and the diffusion regions form the source and drain regions of the transistors, with each diffusion region serving up to four transistors or cells. This patent teaches the basic concept of a double polysilicon array having two sets of intersecting gates forming a plurality of interconnecting field effect transistors (FET) within a matrix of alternating source and drain regions. The array uses continuous angled first-level metal lines to interconnect all of the aligned source, or drain, regions along diagonals. Both depletion read only storage (ROS) and NOR ROS arrays are described. In this layout, all drain nodes are connected together in pairs. Hence, two devices are connected to one output. There are two independent circuits, that is, there are two output nodes.